{"id":8971,"date":"2021-12-09T20:50:00","date_gmt":"2021-12-09T19:50:00","guid":{"rendered":"https:\/\/monodes.com\/predaelli\/?p=8971"},"modified":"2021-12-09T15:01:41","modified_gmt":"2021-12-09T14:01:41","slug":"intels-secret-plan-to-neutralize-arm","status":"publish","type":"post","link":"https:\/\/monodes.com\/predaelli\/2021\/12\/09\/intels-secret-plan-to-neutralize-arm\/","title":{"rendered":"Intel\u2019s Secret Plan to Neutralize ARM"},"content":{"rendered":"<p><span class=\"bp b fw br au fz ga gb gc gd ge em\"><a class=\"bv bw bx by bz ca cb cc bb cd gf cg gg gh\" href=\"https:\/\/erik-engheim.medium.com\/?source=post_page-----c2c5e53a14d-----------------------------------\" rel=\"noopener follow\">Erik Engheim<\/a><\/span> was pondering on <em><a href=\"https:\/\/medium.com\/codex\/intels-secret-plan-to-destroy-arm-c2c5e53a14d\">Intel\u2019s Secret Plan to Neutralize ARM | CodeX.<\/a><\/em><\/p>\n<p>I think he missed an important point, namely the fact that <a href=\"https:\/\/en.wikipedia.org\/wiki\/RISC-V\">RISC-V<\/a> is an <span class=\"js-about-item-abstr\">open standard: <\/span><\/p>\n<blockquote><p>Unlike most other ISA designs, the RISC-V ISA is provided under <a class=\"mw-redirect\" title=\"Open source license\" href=\"https:\/\/en.wikipedia.org\/wiki\/Open_source_license\">open source licenses<\/a> that do not require fees to use<\/p><\/blockquote>\n<p>x86 beated all RISCs during the 80ties and 90ties because its ecosystem was more &#8220;accessible&#8221; than other ISAs. I wouldn&#8217;t underestimate the importance of a shared ecosystem.<\/p>\n<p><!--more--><!--nextpage--><\/p>\n<blockquote>\n<div class=\"\">\n<h1 id=\"3656\" class=\"dn do dp dq b dr ds dt du dv dw dx dy dz ea eb ec ed ee ef eg eh ei ej ek el em\" data-selectable-paragraph=\"\">An Intel Strategy to Neutralize ARM<\/h1>\n<\/div>\n<div class=\"\">\n<h2 id=\"8a7b\" class=\"en do dp bp b eo ep eq er es et eu ev ew ex ey ez fa fb fc fd fe\" data-selectable-paragraph=\"\">With x86 on life support, how will Intel stay relevant in the years to come? Will they be able to keep up with Apple\u2019s M1 lineup?<\/h2>\n<div class=\"ff\">\n<div class=\"n fg fh fi fj\">\n<div class=\"o n\">\n<div>\n<div class=\"fk fl fm\">\n<div class=\"fn n fo o p t fp fq fr fs ft dg\"><\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<div>\n<div class=\"fk fl fm\"><img data-recalc-dims=\"1\" loading=\"lazy\" decoding=\"async\" class=\"s fu fm fl\" src=\"https:\/\/i0.wp.com\/monodes.com\/predaelli\/wp-content\/uploads\/sites\/4\/2021\/12\/01Y9ylHZ8csOxgZr7.jpg?resize=48%2C48&#038;ssl=1\" alt=\"Erik Engheim\" width=\"48\" height=\"48\"\/><\/div>\n<\/div>\n<div class=\"fv aj s\">\n<div class=\"n\">\n<div>\n<div class=\"fx n o fy\"><span class=\"bp b fw br au fz ga gb gc gd ge em\"><a class=\"bv bw bx by bz ca cb cc bb cd gf cg gg gh\" href=\"https:\/\/erik-engheim.medium.com\/?source=post_page-----c2c5e53a14d-----------------------------------\" rel=\"noopener follow\">Erik Engheim<\/a><\/span><\/p>\n<div class=\"fv n\"><\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<div class=\"gy s\">\n<div>\n<div>\n<div class=\"gw\" role=\"tooltip\" aria-hidden=\"false\" aria-describedby=\"247\" aria-labelledby=\"247\">\n<div class=\"s\"><\/div>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n<div><a class=\"bv bw bx by bz ca cb cc bb cd gf cg gg gh\" href=\"https:\/\/medium.com\/codex\/intels-secret-plan-to-destroy-arm-c2c5e53a14d?source=post_page-----c2c5e53a14d-----------------------------------\" rel=\"noopener follow\">Nov 15<\/a> \u00b7 7 min read<\/div>\n<div class=\"n o\">\n<div class=\"hv s ap\">\n<div>\n<div class=\"gw\" role=\"tooltip\" aria-hidden=\"false\" aria-describedby=\"100\" aria-labelledby=\"100\"><\/div>\n<\/div>\n<\/div>\n<\/div>\n<div class=\"hv s ap\">\n<div>\n<div class=\"gw\" role=\"tooltip\" aria-hidden=\"false\" aria-describedby=\"101\" aria-labelledby=\"101\"><\/div>\n<\/div>\n<\/div>\n<div class=\"hv s ap\">\n<div>\n<div class=\"gw\" role=\"tooltip\" aria-hidden=\"false\" aria-describedby=\"102\" aria-labelledby=\"102\"><\/div>\n<\/div>\n<\/div>\n<div class=\"s ap\">\n<div>\n<div class=\"gw\" role=\"tooltip\" aria-hidden=\"false\" aria-describedby=\"103\" aria-labelledby=\"103\"><\/div>\n<\/div>\n<\/div>\n<div class=\"hy s\"><\/div>\n<div class=\"s\">\n<div class=\"gw\" aria-hidden=\"false\"><\/div>\n<\/div>\n<figure class=\"ia ib ic id ie if ct cu paragraph-image\">\n<div class=\"ig ih fk ii aj ij\" tabindex=\"0\" role=\"button\">\n<div class=\"ct cu hz\"><img loading=\"lazy\" decoding=\"async\" class=\"aj ik il\" role=\"presentation\" src=\"https:\/\/miro.medium.com\/max\/700\/0*RFNw6y3cC5HDC_HF\" alt=\"\" width=\"700\" height=\"467\"\/><\/div>\n<\/div><figcaption class=\"im in cv ct cu io ip bp b fw br fe\" data-selectable-paragraph=\"\">Photo by <a class=\"bv iq\" href=\"https:\/\/unsplash.com\/@grstocks?utm_source=medium&amp;utm_medium=referral\" target=\"_blank\" rel=\"noopener ugc nofollow\">GR Stocks<\/a> on <a class=\"bv iq\" href=\"https:\/\/unsplash.com?utm_source=medium&amp;utm_medium=referral\" target=\"_blank\" rel=\"noopener ugc nofollow\">Unsplash<\/a><\/figcaption><\/figure>\n<p id=\"410c\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">Disclaimer, this is pure speculation, based on the moves we have seen Intel making and where the industry is heading. I don\u2019t have any secret backchannel access to Intel board room decisions.<\/p>\n<p id=\"1f1f\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">Further, I don\u2019t believe Intel themselves have any hashed-out plan themselves. Instead, I suspect Intel is evaluating several strategies. Thus this is more of an attempted prediction of what I think will emerge as Intel\u2019s long-term strategy.<\/p>\n<p id=\"777b\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">I know a lot of you would probably say: \u201cHold on, Intel is currently kings of the chip industry. They dominate data centers, PC laptops, and desktops. So why do they need to change?\u201d<\/p>\n<p id=\"2d70\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">But there is currently a rebellion brewing in the kingdom of chips. Things are not what they used to be. It is easy to dismiss Apple as a minor player since it has a mere <a class=\"bv iq\" href=\"https:\/\/9to5mac.com\/2021\/07\/13\/mac-market-share-q2-2021\/\" target=\"_blank\" rel=\"noopener ugc nofollow\">8.5% of the PC market<\/a>. However, the PC market is about 270 million units sold each year, and Intel dominates this market. So how can Apple\u2019s M1 chip make a dent in this?<\/p>\n<p id=\"04e9\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">What people forget is that smartphones and tablets today are extremely powerful. An iPad today will likely outperform a lot of the lower-end PCs. An iPhone can beat an Intel-based Apple laptop on video encoding. Thus arbitrarily drawing up a line between these devices and PCs doesn\u2019t always make that much sense. Apple sells more than 280 million iPads, iPhones, and Macs each year. Hence Apple Silicon is a bigger market than the PC market. Remember, the M1 is a tweaked variant of Apple\u2019s iPad and iPhone chips. Intel isn\u2019t selling chips to smartphones and tablets. That means they are starting to lose the volume game. Things are not as rosy in the kingdom of Intel as they may seem.<\/p>\n<p id=\"f9af\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">If Intel cannot supply chips to the important tablet and smartphone market, they are significantly disadvantaged. And now they are getting into more trouble as Apple has shown what ARM can do for laptops. Nvidia, Qualcomm, and others are gearing up to match Apple and make desktop-class ARM chips. Amazon and Oracle are already starting to use ARM chips in their data centers. Amazon created their Graviton2 chips in cooperation with ARM. Ampere technologies are making ARM chips for Oracle.<\/p>\n<p id=\"8e93\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">It looks quiet before the storm, but a storm is coming, and Intel knows it has to get ready for what is coming or get rendered obsolete.<\/p>\n<h1 id=\"34f7\" class=\"mb mc dp bp kp md me iv mf mg mh iy mi mj mk ml mm mn mo mp mq mr ms mt mu mv em\" data-selectable-paragraph=\"\">Innovators Dilemma<\/h1>\n<p id=\"d0b3\" class=\"ir is dp it b eo mw iv iw er mx iy iz ja my jc jd je mz jg jh ji na jk jl jm dh em\" data-selectable-paragraph=\"\">So what can Intel do? They could begin to make their own ARM chips. However, that is extremely risky, as I have elaborated before <a class=\"bv iq\" href=\"https:\/\/erik-engheim.medium.com\/intel-arm-and-the-innovators-dilemma-a9ebd20ea200\" rel=\"noopener\">Intel, ARM, and the Innovators Dilemma<\/a>.<\/p>\n<p id=\"6254\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">Intel will vindicate an architecture they don\u2019t control and where their competitors have a head start by going all-in on ARM. If Intel is too successful in making an ARM chip, they kill their own profitable x86 business. On the other hand, if they make a too weak ARM chip, they will remain irrelevant in this new emerging ARM-dominated world.<\/p>\n<p id=\"e85f\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">So what can Intel exactly do to fight what seems so inevitable?<\/p>\n<h1 id=\"6fb9\" class=\"mb mc dp bp kp md me iv mf mg mh iy mi mj mk ml mm mn mo mp mq mr ms mt mu mv em\" data-selectable-paragraph=\"\">Betting on the RISC-V Dark Horse<\/h1>\n<p id=\"334d\" class=\"ir is dp it b eo mw iv iw er mx iy iz ja my jc jd je mz jg jh ji na jk jl jm dh em\" data-selectable-paragraph=\"\">A clue to what Intel is up to is their <a class=\"bv iq\" href=\"https:\/\/www.tomshardware.com\/news\/intel-failed-to-buy-sifive\" target=\"_blank\" rel=\"noopener ugc nofollow\">attempted acquisition of SiFive<\/a>. They put $2 billion on the table, but it wasn\u2019t enough. Yet this isn\u2019t game over. Instead, Intel has started a new <a class=\"bv iq\" href=\"https:\/\/www.crn.com\/news\/components-peripherals\/intel-ends-talks-to-acquire-arm-rival-sifive-for-now-report?itc=refresh\" target=\"_blank\" rel=\"noopener ugc nofollow\">RISC-V development platform<\/a> and invested in SiFive.<\/p>\n<p id=\"3c1d\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">Most likely, Intel will throw more money on the table in the future. However, I bet that they want to see RISC-V develop further before committing to even more money.<\/p>\n<p id=\"1d43\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">The question, however, is why RISC-V? Why not just stick with x86 if not going for ARM. And what makes RISC-V more attractive than ARM for Intel?<\/p>\n<p id=\"7e0d\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">x86 is essentially a legacy CISC chip. It spends a ton of transistors to turn its CISC-like exterior into something that looks more RISC-like internally. That eats up power and transistors. However, that doesn\u2019t matter that much for large, powerful chips where transistors allocated to branch prediction, out-of-order execution, large caches, etc., dwarfs the transistor tax imposed by the legacy x86 instruction set. That is why Intel is still relevant on the desktop and in data centers.<\/p>\n<p id=\"22bb\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">However, this also explains why Intel is mainly irrelevant for embedded devices and smartphones. Once you make smaller, simpler chips, the x86 tax starts to become a more significant fraction of the total transistor count of the chip. Thus x86 just cannot compete against RISC chips like ARM in the embedded space. Why does this matter?<\/p>\n<p id=\"0361\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">The x86 market is by <a class=\"bv iq\" href=\"https:\/\/www.tomshardware.com\/news\/arm-6-7-billion-chips-per-quarter\" target=\"_blank\" rel=\"noopener ugc nofollow\">various estimates<\/a> a maximum of 350 million CPUs per year. While something like 25 billion ARM CPUs is sold each year.<\/p>\n<p id=\"d564\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">To have a fighting chance in this market, you need a chip that can offer high performance per watt and scale down well. Intel could go ARM but risk making a me-too product. While riskier, there is a potential for bigger rewards by going RISC-V.<\/p>\n<p id=\"40ab\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">None of the really big chip makers are yet in RISC-V, but there are many promising signs that RISC-V may be capable of outcompeting ARM on performance per watt. For example, you got <a class=\"bv iq\" href=\"https:\/\/arstechnica.com\/gadgets\/2020\/12\/new-risc-v-cpu-claims-recordbreaking-performance-per-watt\/\" target=\"_blank\" rel=\"noopener ugc nofollow\">Micro Magic<\/a> making a RISC-V chip which is supposed to set a record performance per watt, consuming a measly 69 mWatt.<\/p>\n<p id=\"0776\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">If you look at, e.g., Cortex-A5 ARM processor and compare it with RISC-V Rocket processor with similar cache and performance, the die size of the RISC-V is half that of the ARM processor. That has major implications because chip costs grow with the square of the die area. Thus at the same volume of a production, a RISC-V chip will be 4x cheaper than this ARM processor.<\/p>\n<p id=\"d9bd\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">How does RISC-V pull this off? 32-bit ARM has about 500 instructions, while 64-bit ARM has about 1000 instructions. A RISC processor with all the most typical features has only 122 instructions (RV32G). Why so few? RISC-V is extension based. A minimal RISC-V CPU only needs to support 47 instructions. Thus if you want to target simpler markets you don\u2019t necessarily need as many instructions. RISC-V can simply be tailored better than an ARM chip. For small embedded CPUs keeping the number of instructions low pays off because it means you require fewer transistors to make the chip.<\/p>\n<p id=\"574c\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">However, this also matters for specialized hardware such as accelerators for machine learning. <a class=\"bv iq\" href=\"https:\/\/www.esperanto.ai\/technology\/\" target=\"_blank\" rel=\"noopener ugc nofollow\">Esperanto Technologies<\/a>.g. build large chips for Machine Learning based on having lots of RISC-V cores. To squeeze in many cores that can work in parallel, you need them to be simple with a low transistor count. To do that, you need a small instruction set. Neither ARM nor Intel can deliver that.<\/p>\n<h2 id=\"be1e\" class=\"nb mc dp bp kp nc nd eq mf ne nf et mi eu ng ew mm ex nh ez mq fa ni fc mu nj em\" data-selectable-paragraph=\"\">Establish a Beachhead<\/h2>\n<p id=\"2ef6\" class=\"ir is dp it b eo mw iv iw er mx iy iz ja my jc jd je mz jg jh ji na jk jl jm dh em\" data-selectable-paragraph=\"\">RISC-V has inherent advantages which will allow Intel to compete in the opposite end of the market where they cannot compete at the moment with x86. In addition, by building a presence in the embedded space, they can build up their skill and competency on RISC-V, so that by the time x86 no longer can hold back the ARM tide wave on the desktop and server, Intel may already have built up the skill and experience with RISC-V to begin offering powerful RISC-V chips which can compete with ARM on the desktop and server market.<\/p>\n<p id=\"1e1e\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">Please note this is not something I see happening in a while. Building up this skill will take a lot of time. This could easily be a ten-year project. Intel knows that a lot of businesses cannot immediately transition to ARM even if ARM chips end up cheaper and faster because it takes time to transition software and platforms. That will buy Intel some time. Their market share will decline, they will not get destroyed overnight.<\/p>\n<p id=\"85b6\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">However, there is no way x86 can defend itself against ARM for a whole 5\u201310 years longer. Thus Intel needs to establish a plan-B. I bet that this will be RISC-V, but that the moment this is not their full commitment. This is a significant strategic choice, and they need to be sure they are making the right choice.<\/p>\n<p id=\"a616\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">Keep in mind this is a typical large conservative company. Look at how big automakers reacted to Tesla. Their EV investments were half-hearted for years. You can bet Intel RISC-V investments will be half-hearted for a while before it becomes crystal clear to them and the industry at large that there is no way without going full in on RISC-V.<\/p>\n<h1 id=\"bb79\" class=\"mb mc dp bp kp md me iv mf mg mh iy mi mj mk ml mm mn mo mp mq mr ms mt mu mv em\" data-selectable-paragraph=\"\">The Dangers<\/h1>\n<p id=\"0454\" class=\"ir is dp it b eo mw iv iw er mx iy iz ja my jc jd je mz jg jh ji na jk jl jm dh em\" data-selectable-paragraph=\"\">However, there are major dangers here. We can make parallel to Blackberry, Nokia, Windows Phone, and Android. Intel is in a situation not entirely unlike Nokia, when it dominated the mobile phone space. Nokia was like Intel used to control all the parts of their product. They did not want to license Android, just like Intel does not want to license ARM. Nokia figured that would undermine their unique advantages.<\/p>\n<p id=\"69ba\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">The choice thus became to make an unconventional choice and go for Windows Phone. That proved a disaster. The Android momentum was too large, and Windows Phone was too late to the market. Likewise, the ARM momentum may be too large to stop at this point, and going for RISC-V may end up being akin to going for Windows Phone.<\/p>\n<p id=\"5843\" class=\"ir is dp it b eo iu iv iw er ix iy iz ja jb jc jd je jf jg jh ji jj jk jl jm dh em\" data-selectable-paragraph=\"\">You end up with a platform that doesn\u2019t have enough vendor support compared to the competition. Yet, my bet is this will be different. RISC-V has momentum regardless of Intel. That was not the case with Windows Phone. RISC-V is sufficiently different from the competition to matter. Windows Phone was not a big enough improvement to be worth it to most people.<\/p>\n<\/blockquote>\n","protected":false},"excerpt":{"rendered":"<p class=\"excerpt\">Erik Engheim was pondering on Intel\u2019s Secret Plan to Neutralize ARM | CodeX. I think he missed an important point, namely the fact that RISC-V is an open standard: Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use x86 beated all RISCs during&hellip;<\/p>\n<p class=\"more-link-p\"><a class=\"more-link\" href=\"https:\/\/monodes.com\/predaelli\/2021\/12\/09\/intels-secret-plan-to-neutralize-arm\/\">Read more &rarr;<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"inline_featured_image":false,"jetpack_post_was_ever_published":false,"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_memberships_contains_paid_content":false,"activitypub_content_warning":"","activitypub_content_visibility":"","activitypub_max_image_attachments":4,"activitypub_interaction_policy_quote":"anyone","activitypub_status":"","footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":true,"jetpack_social_options":{"image_generator_settings":{"template":"highway","default_image_id":0,"font":"","enabled":false},"version":2}},"categories":[1],"tags":[],"class_list":["post-8971","post","type-post","status-publish","format-standard","hentry","category-senza-categoria"],"jetpack_publicize_connections":[],"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"jetpack_shortlink":"https:\/\/wp.me\/p6daft-2kH","jetpack-related-posts":[{"id":7805,"url":"https:\/\/monodes.com\/predaelli\/2020\/12\/06\/un-chip-risc-v-promette-di-demolire-apple-m1-ecco-chi-ce-dietro-e-di-cosa-si-tratta\/","url_meta":{"origin":8971,"position":0},"title":"Un chip RISC-V promette di demolire Apple M1. Ecco chi c&#8217;\u00e8 dietro e di cosa si tratta","author":"Paolo Redaelli","date":"2020-12-06","format":false,"excerpt":"La californiana Micro Magic afferma di aver messo a punto un core basato su ISA RISC-V che non teme confronti, nemmeno l'interessantissimo Apple M1 su base ARM, grazie a frequenze intorno ai 5 GHz e consumi estremamente ridotti. Un chip RISC-V promette di demolire Apple M1. Ecco chi c'\u00e8 dietro\u2026","rel":"","context":"In &quot;Hardware&quot;","block_context":{"text":"Hardware","link":"https:\/\/monodes.com\/predaelli\/category\/hardware\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]},{"id":9233,"url":"https:\/\/monodes.com\/predaelli\/2022\/04\/02\/the-first-risc-v-portable-computer-is-now-available\/","url_meta":{"origin":8971,"position":1},"title":"The first RISC-V portable computer is now available","author":"Paolo Redaelli","date":"2022-04-02","format":false,"excerpt":"The DevTerm R-01 is a RISC-V based \"slabtop\" computer. The first RISC-V portable computer is now available Well, it's not exactly on par on Apple M1, but this machine fills an entirely different niche. \u00a0","rel":"","context":"In &quot;Hardware&quot;","block_context":{"text":"Hardware","link":"https:\/\/monodes.com\/predaelli\/category\/hardware\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]},{"id":9740,"url":"https:\/\/monodes.com\/predaelli\/2022\/10\/16\/ox64-the-8-risc-v-single-board-computer\/","url_meta":{"origin":8971,"position":2},"title":"Ox64: the 8$ RISC-V single board computer","author":"Paolo Redaelli","date":"2022-10-16","format":false,"excerpt":"Ox64 \u2013 a sub $10 Linux capable single board computer from Pine64 people. For 8$ you get 3 RISC-V cores: 64-bit, 32-bit and low power core, plus 64Mb of RAM. That's interesting!","rel":"","context":"In &quot;Hardware&quot;","block_context":{"text":"Hardware","link":"https:\/\/monodes.com\/predaelli\/category\/hardware\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]},{"id":5226,"url":"https:\/\/monodes.com\/predaelli\/2019\/02\/14\/you-can-now-build-a-risc-v-pc-that-runs-fedora-linux-with-an-fpga\/","url_meta":{"origin":8971,"position":3},"title":"You Can Now Build a RISC-V PC That Runs Fedora Linux with an FPGA","author":"Paolo Redaelli","date":"2019-02-14","format":"status","excerpt":"https:\/\/blog.hackster.io\/you-can-now-build-a-risc-v-pc-that-runs-fedora-linux-with-an-fpga-97cd5789b28?fbclid=IwAR0TrxxFqWlxARY0y3jSM9su8XOHJMQosBdcdxF05SZvxwaYY7ZSuRZ3k90 I can't wait to see a complete system using RISC-V","rel":"","context":"In &quot;Senza categoria&quot;","block_context":{"text":"Senza categoria","link":"https:\/\/monodes.com\/predaelli\/category\/senza-categoria\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]},{"id":5115,"url":"https:\/\/monodes.com\/predaelli\/2019\/01\/08\/raspberry-pi-becomes-a-member-of-the-risc-v-foundation\/","url_meta":{"origin":8971,"position":4},"title":"Raspberry Pi Becomes a Member of the RISC-V Foundation","author":"Paolo Redaelli","date":"2019-01-08","format":false,"excerpt":"https:\/\/blog.hackster.io\/raspberry-pi-becomes-a-member-of-the-risc-v-foundation-11f06aecc241?fbclid=IwAR02zsBHEyknETTlDPyoiJe_KY8jdRIV8DpdHvI86ieQiI_wtcig4LhEAME I can't wait for it!","rel":"","context":"In &quot;Senza categoria&quot;","block_context":{"text":"Senza categoria","link":"https:\/\/monodes.com\/predaelli\/category\/senza-categoria\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]},{"id":5627,"url":"https:\/\/monodes.com\/predaelli\/2019\/06\/02\/nlnet-funds-development-of-a-libre-risc-v-3d-cpu\/","url_meta":{"origin":8971,"position":5},"title":"NLNet Funds Development of a Libre RISC-V 3D CPU","author":"Paolo Redaelli","date":"2019-06-02","format":"link","excerpt":"Well we live interesting times: This processor, which will be quad core dual issue 800mhz RV64GC and capable of running full GNU\/Linux SMP OSes, with 720p video playback and embedded level 25fps 3D performance in around 2.5 watts at 28nm, is designed to address that imbalance. Links and details on\u2026","rel":"","context":"In &quot;Debian&quot;","block_context":{"text":"Debian","link":"https:\/\/monodes.com\/predaelli\/category\/debian\/"},"img":{"alt_text":"","src":"","width":0,"height":0},"classes":[]}],"jetpack_likes_enabled":true,"_links":{"self":[{"href":"https:\/\/monodes.com\/predaelli\/wp-json\/wp\/v2\/posts\/8971","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/monodes.com\/predaelli\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/monodes.com\/predaelli\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/monodes.com\/predaelli\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/monodes.com\/predaelli\/wp-json\/wp\/v2\/comments?post=8971"}],"version-history":[{"count":0,"href":"https:\/\/monodes.com\/predaelli\/wp-json\/wp\/v2\/posts\/8971\/revisions"}],"wp:attachment":[{"href":"https:\/\/monodes.com\/predaelli\/wp-json\/wp\/v2\/media?parent=8971"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/monodes.com\/predaelli\/wp-json\/wp\/v2\/categories?post=8971"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/monodes.com\/predaelli\/wp-json\/wp\/v2\/tags?post=8971"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}